CACHABLEEN=CACHABLEEN_0, APAREN=APAREN_0, BUFFERABLEEN=BUFFERABLEEN_0, READADDROPT=READADDROPT_0
AHB Bus Control Register
| APAREN | Parallel mode enabled for AHB triggered Command (both read and write) . 0 (APAREN_0): Flash will be accessed in Individual mode. 1 (APAREN_1): Flash will be accessed in Parallel mode. |
| CACHABLEEN | Enable AHB bus cachable read access support. 0 (CACHABLEEN_0): Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer. 1 (CACHABLEEN_1): Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first. |
| BUFFERABLEEN | Enable AHB bus bufferable write access support. This field affects the last beat of AHB write access, refer for more details about AHB bufferable write. 0 (BUFFERABLEEN_0): Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus ready after all data is transmitted to External device and AHB command finished. 1 (BUFFERABLEEN_1): Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is granted by arbitrator and will not wait for AHB command finished. |
| PREFETCHEN | AHB Read Prefetch Enable. |
| READADDROPT | AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation. 0 (READADDROPT_0): There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is wordaddressable. 1 (READADDROPT_1): There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB burst required to meet the alignment requirement. |